Modern polyphase DC motors have become commonplace in precision equipment such as hard disk drives of modern personal computer and workstation equipment, where the requirements of positional accuracy and operational speed are quite stringent. As a result, control circuitry for such motors has become quite sophisticated in ensuring rapid and uniform drive of the disk drive motors. "Glitches" and other nonlinearities such as torque ripple are highly undesirable in the drive of these motors, as they reduce motor performance, increase undesired acoustical noise, and increase the rate of motor wear.
Conventional polyphase DC motors are powered by the application of current to one or more selected stator coils of the motor according to a predetermined sequence to produce a varying magnetic field that rotates a permanent magnet rotor. The sequence in which the current is applied to the stator coils is generally referred to as the commutation sequence, as the drive current is commutated among the various stator coils in the sequence. This commutation produces electrical transients, however, as a result of the inductive nature of the stator coils; these transient effects are manifest in non-uniformity (i.e., "ripple") in the torque applied to the motor, and also in electromagnetic interference ("EMI") generated by the commutation.
Various techniques have previously been used to reduce the electrical transients from commutation, and thus reduce torque ripple and EMI. One such technique is described in U.S. Pat. No. 5,191,269, issued Mar. 2, 1993, assigned to SGS-Thomson Microelectronics, Inc. and incorporated herein by this reference. In this technique, a current integrator is used to control the gates of field-effect drive transistors in such a manner as to reduce the slew rate, or time rate of change of voltage, at the stator coil when the drive transistor for that coil is turned off.
Referring now to FIG. 1, the motor drive circuitry in this prior arrangement will now be described in detail. Motor 10 includes stator coils 4A, 4B, 4C, through which current is driven in operation of the motor to turn the rotor (not shown). Each of stator coils 4A, 4B, 4C is connected to the drain of a corresponding field-effect drive transistor 8A, 8B, 8C, respectively, at nodes A, B, C. In this example, center tap CT of motor 10 is biased to V.sub.cc through transistor 9 (while line UNI is maintained high), and as such drive transistors 8A, 8B, 8C are "low-side" drivers, as they control the current conducted to ground through its corresponding stator coil 4A, 4B, 4C. The sources of each of drive transistors 8A, 8B, 8C are connected in common to one end of a sense resistor 6, which has its other end connected to ground.
The gates of drive transistors 8A, 8B, 8C in this prior arrangement are driven by a buffer amplifier 12A, 12B, 12C under control of an error amplifier 2 that is implemented, in this example, as an operational transconductance amplifier (OTA). The output of error amplifier 2 is connected to switches 5A, 5B, 5C, each of which are connected to the input of its corresponding respective buffer amplifier 12A, 12B, 12C. Switches 5A, 5B, 5C are controlled by a conventional commutation sequencer circuit (not shown) which produces an active signal on lines SWA, SWB, SWC, respectively, according to the desired commutation sequence. Error amplifier 2 receives a command signal on line IN, and a feedback signal on line FB from the top end of sense resistor 6, and produces an output current proportional to the differential voltage between the command signal on line IN and the sensed voltage on line FB (which corresponds to the sum of the drive currents through coils 4A, 4B, 4C). In this way, error amplifier 2 controls the drive of motor 10 according to an external control signal, with the balanced condition being that the feedback voltage on line FB, corresponding to drive current sensed by sense resistor 6, equals that commanded by the signal on line IN.
In operation, if stator coil 4A is to conduct current in a specific commutation phase, for example, line SWA will be driven high by the commutation sequencer, and lines SWB, SWC will be driven low. The output of error amplifier 2, indicating the amount of drive current to be driven to the selected stator coil 4, will then be applied to the input of buffer amplifier 12A, which in turn turns on low side drive transistor 8A to the extent indicated by error amplifier 2. Current will then be conducted from V.sub.cc through transistor 9, center tap CT and coil 4A to the extent allowed by drive transistor 8A. If the next commutation phase requires stator coil 4B to conduct rather than stator coil 4A, line SWB will be driven high and line SWA (and line SWC) will be driven low, turning on transistor 8B and turning off transistor 8A, thus conducting current through stator coil 4B rather than stator coil 4A. The sequence continues in the same manner, with stator coil 4C next conducting, to rotate the motor at the desired speed indicated by the command signal on line IN.
While this example illustrates operation of motor 10 in a unipolar mode, motor 10 may also or instead be driven in the well-known bipolar mode, in which center tap CT will not be driven and in which high-side driver transistors will drive each of nodes A, B, C in sequence in combination with low-side driver transistors 8A, 8B, 8C. In this mode, two stator coils 4 will be driven in each commutation phase, to the extent controlled by one of the drive transistors (generally the low-side drive transistors 8), with one stator coil 4 sourcing current toward center tap CT and with the other stator coil 4 sinking current therefrom.
In the arrangement of FIG. 1, as described in the above-incorporated U.S. Pat. No. 5,191,269, a current integrating function is provided to reduce voltage transients at nodes A, B, C that result when the corresponding respective drive transistor 8A, 8B, 8C is turned off in commutation. These transients result from the inability to instantaneously change the current through an inductor, such as through stator coils 4A, 4B, 4C. The current integrating is implemented by current sources 14A, 14B, 14C, each connected to the input of a corresponding respective buffer amplifier 12A, 12B, 12C, and by capacitors 7A, 7B, 7C connected between nodes A, B, and C, respectively, and the input to the corresponding buffer amplifier 12A, 12B, 12C, respectively. The effect of current sources 14 and capacitors 7 is to limit the voltage slew rate at nodes A, B, C when the corresponding drive transistor 8 is turned off.
In brief, referring by way of example to node A, the voltage V.sub.A at node A will obey the following relationship when transistor 8A is turned off: ##EQU1## where i.sub.14A is the current sourced by current source 14A, and where C.sub.7 is the capacitance of capacitor 7A. Accordingly, the provision of current sources 14 and capacitors 7 serve well to reduce the voltage slew rate at stator coils 4 during commutation.
Relative to the arrangement of FIG. 1, it has been observed, however, that voltage transients still remain to some extent at those nodes for which the corresponding drive transistor is turning on. FIG. 2 illustrates the operation of the circuit of FIG. 1 at the commutation between stator coil 4A being driven to stator coil 4B being driven. At time t.sub.0, the voltage V.sub.A at node A is low, the voltage V.sub.B at node B is high, the current I.sub.A through stator coil 4.sub.A is at a high level and the current I.sub.B through stator coil 4.sub.B is zero, given that transistor 8A is on and transistor 8B is off. The operation of sense resistor 6 with error amplifier 2 means that the drive currents are controlled so that the sum of the coil currents i.sub.A, i.sub.B, i.sub.C is constant (i.sub.C being zero in this example of commutation from coil 4A to coil 4B).
At time t.sub.1, line SWA goes low and line SWB goes high, to turn off transistor 8A and turn on transistor 8B. Because of the reduced slew rate provided by current source 14A and capacitor 7A noted above, the voltage V.sub.A slowly ramps up toward its eventual high voltage, at a rate corresponding to the ratio i.sub.14A /C.sub.7, as noted above; qualitatively, the instantaneous current through stator coil 4A is absorbed by capacitor 7A in such a way as to prevent a positive-going voltage spike at node A at t.sub.1.
However, since the current I.sub.B through stator coil 4B at time t.sub.0 is zero, and since this current cannot instantaneously change at time t.sub.1, transistor 8B will not be conducting current at such time as it is turned on at time t.sub.1. In addition, the current provided at the output of error amplifier 2 is also quite large, and is substantially absorbed by capacitor 7B when switch 5B is turned on at time t.sub.1. These events result in the drain voltage of transistor 8B immediately collapsing low due to the lack of drain-to-source current and to the rapid charging of capacitor 7B. This rapid transient results in significant ringing of the voltage V.sub.B at node B, as shown in FIG. 2, and thus in a significant amount of undesired electromagnetic interference (EMI).
It is therefore an object of the present invention to provide a circuit and method for reducing the turn-on transients in the commutation of a polyphase DC motor.
It is a further object of the present invention to accomplish these results by limiting the voltage slew rate at the coils during turn-on.
It is a further object of the present invention to provide such circuitry which presents a relatively low input impedance to the error amplifier after the period of limited voltage slew rate in a commutation phase.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.